1. Field of the Invention
This invention relates to a semiconductor memory device including a plurality of memory cells each including a transistor and a capacitor and, more particularly, to such a semiconductor memory device which is improved both in integration degree and operational reliability.
2. Description of the Prior Art
FIG. 4A is a block diagram showing an example of a dynamic random access memory (RAM) device, and FIG. 4B is a circuit diagram showing a RAM cell. Referring to these figures, an array of memory cells 101 includes a plurality of memory cells arranged in a matrix configuration. These memory cells are arranged at the points of intersection between a plurality of word lines 110 connected to an X address buffer decoder 102 and a plurality of bit lines 107 connected to a Y address buffer decoder 103. Each memory cell includes a field effect transistor 108 and a capacitor 109. Each capacitor 109 has its one electrode 111 connected to the field effect transistor 108 and is called a storage node, and the other 112 is called a cell plate or common electrode.
During data writing, the field effect transistor 108 is turned on as a predetermined potential is applied to the word line 110, such that the charges supplied from the bit line 107 are stored in the capacitor 109. Conversely, during data read-out, the field effect transistor 108 is turned on as a predetermined potential is applied to the word line, such that the charges stored in the capacitor are taken out via the bit line 107.
When a memory cell to which data should be written or from which data should be read out is selected, one word line 110 is selected by the X address buffer decoder 102 and one bit line 107 is selected by the Y address buffer decoder 103. That is, that memory cell which is arranged at the point of intersection between the selected word line 110 and the selected bit line 107 is selected.
A read/write control circuit 104 controls data read out or writing in dependence upon a read/write control signal R/W. During data writing, an input data Din is applied to the selected memory cell via the read/write control circuit 104 and a sense amplifier 105. During data read-out, the data stored in the selected memory cells are detected and amplified by the sense amplifier 105 so as to be taken out via a data output buffer 106 as output data Dout.
Recently, for improving the integration degree and the operational reliability of a dynamic RAM device, a variety of trench type capacitors for memory cells have been proposed. FIG. 5 is a diagrammatic sectional view showing a pair of memory cells having trench type capacitors as disclosed in Japanese Patent Laying-Open Gazette No. 88555/1986. In this figure, a trench h is formed on a planar surface of a p-type semiconductor substrate 211 and a pair of capacitors are formed in the trench h. A polysilicon region 230, supplied with a reference potential from the substrate 211, acts as a cell plate for the two capacitors and also as a separation region between these two capacitors. Signal charges are stored in a polysilicon storage node 217 arranged along sidewalls of the trench h and having their surface covered by silicon oxide films 218a, 218b. Hence, by forming the trench h to a larger depth, a large storage capacity may be obtained without increasing the planar area occupied by the capacitors.
Each of the pair of n-channel type field effect transistors includes a polysilicon gate electrode 213 connected to the word line, an n-type drain region 214 connected to the bit line, and an n-type source region 215 connected by the polysilicon source electrode 216 to one of the storage nodes 217. Below the n-type source region 215, a p.sup.+ impurity region 212 is formed, by which the source region 215 is isolated from a depletion layer formed on the substrate 211 by the potential of the storage node 217. Hence, the p.sup.+ impurity layer 212 is effective to prevent soft error caused by .alpha. particles.
In the memory cell of FIG. 5, the positive potential with respect to the p type substrate 211 is applied to the gate 213, such that channel region between the n type source 215 and the n type drain 214 is rendered conductive so that data can be written into or read out from the storage node 217.
The memory cell of FIG. 5 is a so-called substrate cell plate type memory cell in which the reference potential is applied from the semiconductor substrate 211 to the cell plate 230. However, with this construction, the noise potential of the semiconductor substrate 211 is reflected directly as the fluctuations in the cell plate potential to lower the noise margin of the memory cell. Moreover, since it is not possible with the substrate cell plate type memory cell to apply a potential different from the predetermined substrate potential to the cell plate 230, the cell plate potential cannot be adjusted in such a manner as to decrease the intensity of the electrical field applied to dielectric film 218a of the capacitor.
M. Kumanoya et al reports in IEEE J. Solid-State Circuits, vol. SC-18, pp 909 to 913 Oct., 1985 that, by applying a potential Vcc/2 (2V) different from the substrate potential Vss (0V) to the cell plate, the intensity of the electrical field applied to the dielectric film of the capacitor is decreased to improve the operational reliability of the memory cell. In this case, the "H" level signal voltage is 4V, and the "L" level signal voltage is 0V. That is, when the substrate potential Vss is applied to the cell plate, the dielectric film of the capacitor must withstand the intensity of the electrical field of 4V, whereas, when the potential Vcc/2 is applied to the cell plate, it is only necessary for the dielectric film to withstand the intensity of electrical field of 2V. This means that a larger thickness of dielectric film of the capacitor is required when the substrate potential is applied to the cell plate, and the thicker dielectric film of the capacitor are not desirable to the higher degree of integration of the RAM device.
Moreover, in FIG. 5, inasmuch as a depletion layer is formed in the substrate 211 due to the potential of the storage node 217, the silicon oxide film 218b practically does not play the role of the dielectric film of the capacitor. In order that not only the silicon oxide film 218a but also the silicon oxide film 218b may act as a dielectric film of the capacitor, it is sufficient to increase the concentration of the p type impurity in the substrate 211. However, when the impurity concentration of the substrate is increased, the threshold voltage of the field effect transistor is undesirably increased.